Electrical Product Agents

LP DDR SDRAM 512Mb

FMD8C16LAx 32*16Mb
- Functionality
- Double-data-rate architecture ; two data transfers per CLK cycle.
- Bidirectional data strobe per byte data (DQS).
- No DLL ; CLK to DQS is not Synchronized.
- Differential CLK inputs( CLK and /CLK ).
- Commands entered on each positive CLK edge.
- DQS edge-aligned with data for Reads; center-aligned with data for Writes.
- Four internal banks for concurrent operation.
- Data masks (DM) for masking write data-one mask per byte.
- Programmable burst lengths : 2, 4, 8, 16.
- Programmable CAS Latency : 2, 3.
- Concurrent auto pre-charge option is supported.
- Auto refresh and self refresh modes.
- Status read register (SRR)
- LVCMOS-compatible inputs. - Configuration
- 32 Meg X 16 (8 Meg X 16 X 4Bank). - Low Power Features
- Low voltage power supply.
- Auto TCSR (Temperature Compensated Self Refresh).
- Partial Array Self Refresh power
-saving mode.
- Deep Power Down Mode.
- Driver Strength Control. FMD8C32LAx 16*32Mb
- Configuration
- 16 Meg X 32 (4 Meg X 32 X 4Bank). - Low Power Features
- Low voltage power supply.
- Auto TCSR (Temperature Compensated Self Refresh).
- Partial Array Self Refresh power
-saving mode.
- Deep Power Down Mode.
- Driver Strength Control.